1. Technical Field
The present invention relates to a semiconductor chip having fuses, and a method of fabricating the same.
2. Related Art
Fuses are introduced into semiconductor devices for various purposes. Memories such as DRAM, for example, introduce the fuses for the purpose of redundancy replacement by which a redundant bit is allowed to operate in place of a fault bit (K. Arndt et al., Reliability of Laser Activated Metal Fuses in DRAMs, 1999 IEEE/CPMT Int'l Electronics Manufacturing Technology Symposium, p. 389-394). In this case, operations of a semiconductor device are tested after the wafer process, and if any fault bit is found, a fuse connected to the fault bit is blown in order to replace such fault bit with a redundant bit.
The fuses are also introduced among a plurality of target logic circuits for the purposes of regulating voltage or adjusting timings of the logic circuits in the semiconductor device. In this case, the internal voltages and timings are measured after the wafer process, and the fuses are blown so as to obtain a desired voltage or timing.
Still another example is such that a plurality of fuses are introduced and respectively correlated to information “1” or “0” depending on whether the fuse has been blown or not, so as to allow discrimination of the semiconductor device. For example, introduction of 128 fuses into every semiconductor chip allows storage of 128-bit information into each semiconductor chip. Allowing every semiconductor chip to hold different information makes it possible to use the fuses as a discriminator or identifier, and makes it possible to identify the individual semiconductor chips.
Japanese domestic re-publication of PCT International Publication for Patent Applications WO98/09327 discloses a technique of fabricating a gate array using an anti-fuse-system FPGA and having logic functions same as those of the FPGA, in which before and after forming the anti-fuse of FPGA, elements and interconnections in common to both of the FPGA and a gate array are formed on the same semiconductor substrate using a common photomask, and in the step of forming the anti-fuse section and contact holes of the correspondent gate array, photomasks specific to the both are used. The photomask specific to the gate array is produced using a pattern data obtained by converting write information for the anti-fuse section of the FPGA into contact hole information for the gate array. This makes it possible to fabricate the gate array having logic functions and performances absolutely same as those of the FPGA, and this reportedly raises an effect typically such that it becomes no more necessary to newly provide an interconnection arrangement step or a timing simulation step when the fabrication transits from FPGA process to gate array process.
The technique disclosed in WO98/09327 is, however, aimed at efficiently fabricate the gate array using the anti-fuse-system FPGA, having the same logic functions therewith, and thus-fabricated gate array has no fuses formed therein, so that the gate array no more allows programmable configuration of the logic circuits.
In the conventional semiconductor device having fuses introduced therein, fuses specified for disconnection are blown by laser irradiation or current supply. Increase in the number of fuses to be blown, therefore, raises a problem of needing more time for blowing the fuses, and of increasing the TAT (turn around time).